Cast【免费下载链接】asc-devkit本项目是CANN 推出的昇腾AI处理器专用的算子程序开发语言原生支持C和C标准规范主要由类库和语言扩展层构成提供多层级API满足多维场景算子开发诉求。项目地址: https://gitcode.com/cann/asc-devkit产品支持情况Ascend 950PR/Ascend 950DT支持Atlas A3 训练系列产品/Atlas A3 推理系列产品不支持Atlas A2 训练系列产品/Atlas A2 推理系列产品不支持Atlas 200I/500 A2 推理产品不支持Atlas 推理系列产品AI Core不支持Atlas 推理系列产品Vector Core不支持Atlas 训练系列产品不支持功能说明头文件路径basic_api/reg_compute/kernel_reg_compute_vec_vconv_intf.h。Cast用于数据类型精度转换将源操作数数据类型转换成目的操作数数据类型能够实现浮点转整数、浮点转浮点、整数转浮点、整数转整数的数据类型转换。转换过程中由于位宽变化、精度变化支持配置如下参数进行功能实现RegLayout源操作数和目的操作数位宽不同时单条指令计算量以位宽更大的数据类型为准RegLayout用于控制位宽小的元素在寄存器中的排布方式。SatMode用于设置饱和与不饱和模式。MaskMergeMode用于指定写入寄存器数据模式mask未选择的元素在dst中置零或保留dst原值。RoundMode用于设置舍入模式。不同数据类型下元素对应的mask位宽不一致在Cast进行类型转换时MaskReg根据输入的源操作数进行有效元素筛选。 图b16到b32类型转换过程和图b32到b16类型转换过程展示了MaskReg和RegLayout同时作用时b16和b32进行类型转换的过程。图1b16到b32类型转换过程图2b32到b16类型转换过程函数原型template typename T DefaultType, typename U DefaultType, const CastTrait trait castTrait, typename S, typename V __simd_callee__ inline void Cast(S dstReg, V srcReg, MaskReg mask);参数说明表 1模板参数说明参数名描述T目的操作数的数据类型。支持的数据类型请参考数据类型。U源操作数的数据类型。支持的数据类型请参考数据类型。traitCastTrait类型类型转换模式结构体。包括RegLayout、SatMode、MaskMergeMode、RoundMode。struct CastTrait {RegLayout layoutMode RegLayout::UNKNOWN;SatMode satMode SatMode::UNKNOWN;MaskMergeMode mrgMode MaskMergeMode::UNKNOWN;RoundMode roundMode RoundMode::UNKNOWN;};使能SatMode生效需与SetCtrlSpr配合使用。不饱和模式和饱和模式的具体配置请参考表5 饱和模式全局或单指令生效配置表。注SetCtrlSpr需在SIMD_VF外调用。S目的操作数的RegTensor类型例如RegTensorfloat由编译器自动推导用户不需要填写。V源操作数的RegTensor类型例如RegTensorint32_t由编译器自动推导用户不需要填写。表 2参数说明参数名输入/输出描述dstReg输出目的操作数。类型为RegTensor。srcReg输入源操作数。类型为RegTensor。mask输入源操作数元素操作的有效指示详细说明请参考MaskReg。注mask会按照输入来筛选。数据类型表 3数据类型组合情况srcdstint4x2_tint16_t、half、bfloat16_tint8_tint16_t、half、int32_tuint8_tuint16_t、half、uint32_tfp4x2_e2m1_tbfloat16_tfp4x2_e1m2_tbfloat16_thifloat8_thalf、floatfp8_e8m0_tbfloat16_tfp8_e5m2_tfloatfp8_e4m3fn_tfloatint16_tint4x2_t、uint8_t、half、int32_t、uint32_t、floatuint16_tuint8_t、uint32_thalfint4x2_t、int8_t、uint8_t、hifloat8_t、int16_t、bfloat16_t、int32_t、floatbfloat16_tfp4x2_e2m1_t、fp4x2_e1m2_t、fp8_e8m0_t、half、int32_t、floatint32_tuint8_t、int16_t、float、int64_tuint32_tuint8_t、int16_t、uint16_tfloathifloat8_t、fp8_e5m2_t、fp8_e4m3fn_t、int16_t、half、bfloat16_t、int32_t、int64_tint64_tint32_t、float返回值说明无约束说明当目的操作数位宽比源操作数小时再MaskReg和RegLayout作用下目的操作数中的无效元素均为0。该指令需配合SetCtrlSpr指令使用通过设置寄存器的值控制Cast的不饱和模式和饱和模式。舍入模式仅在可能导致精度损失且支持该舍入模式的转换中生效具体支持情况请参考关键特性说明。不同类型转换的不饱和与饱和模式的描述有所区别全局或单指令生效配置方法也不同具体内容参考表4 不同类型转换场景的不饱和模式和饱和模式、表5 饱和模式全局或单指令生效配置表。浮点数转浮点数当输出类型float32时只支持不饱和模式。不饱和模式当输出类型为fp8_e4m3fn_t时由于fp8_e4m3fn_t没有inf表示格式所以输出为nan。饱和模式当输出类型为fp8_e5m2_t/fp8_e4m3fn_t时输入nan默认输出为0。如果CTRL[50] 1b1则输出为nan。fp4x2_e2m1_t/fp4x2_e1m2_t数据类型没有inf和nan的定义。对于bfloat16到float4的数据类型转换输入bfloat16类型的值为inf或超出fp4x2_e2m1_t/fp4x2_e1m2_t数据最值范围时会返回对应符号的fp4x2_e2m1_t/fp4x2_e1m2_t最值输入nan时fp4x2_e2m1_t/fp4x2_e1m2_t输出0。对于fp8_e8m0_t类型输入bfloat16_t /-inf或绝对值超出fp8_e8m0_t类型最大值则返回fp8_e8m0_t最大值0b11111110输入bfloat16_t nan输出fp8_e8m0_t nan 0b11111111。整数转整数对于窄数据类型例如int16_t(2Byte)转宽数据类型uint32_t(4Byte)只支持饱和模式输入负数会被饱和成0。特别地int4x2_t/fp4x2_e2m1_t/fp4x2_e1m2_t和b16之间的转换指令会以每2个元素为一对进行读写大转小时mask有效位以偶数位为准。图fp4x2_e2m1_t到bfloat16_t转换过程和图bfloat16_t到fp4x2_e2m1_t转换过程展示了MaskReg和RegLayout同时作用时fp4x2_e2m1_t和bfloat16_t之间的转换。图3fp4x2_e2m1_t到bfloat16_t转换过程图4bfloat16_t到fp4x2_e2m1_t转换过程关键特性说明不同类型转换场景下的不饱和模式和饱和模式表 4不同类型转换场景的不饱和模式和饱和模式场景不饱和模式饱和模式浮点转整数输入数据超过输出类型最值时结果被截断为目标格式的数据宽度保留最低有效位例如输入half值为257输出uint8_t值为1输入为/-inf时则返回输出类型的对应最值输入为nan时返回0。输入数据超过输出类型最值时返回输出类型的对应最值例如输入half值为257输出uint8值为255输入half值为-inf输出uint8_t值为0输入为nan时返回0。浮点转浮点输入数据为nan时输出为nan输入/-inf时输出为/-inf。输入为nan时输出为0输入数据超过输出类型最值时返回输出类型的对应最值。整数转浮点不支持不饱和模式输入为nan时输出为0输入数据超过输出类型最值时返回输出类型的对应最值。该场景默认饱和模式无需配置。整数转整数输入数据会截断为目标数据宽度例如输入int32_t值为256输出uint8_t值为0。输入数据超出目标数据范围会饱和为目标数据最值。不饱和模式和饱和模式配置表 5饱和模式全局或单指令生效配置表全局使能位控制位功能描述CTRL[60] 1b0Reg矢量计算Cast API的trait模板参数中satMode设置为SatMode::NO_SAT。单指令非饱和模式。CTRL[60] 1b0Reg矢量计算Cast API的trait模板参数中satMode设置为SatMode::SAT。单指令饱和模式。CTRL[60] 1b1CTRL[48] 1b1全局非饱和模式浮点数计算和浮点数精度转换。CTRL[60] 1b1CTRL[48] 1b0全局饱和模式浮点数计算和浮点数精度转换。CTRL[60] 1b1CTRL[59] 1b1全局非饱和模式浮点数转整数或整数转整数时的精度转换。CTRL[60] 1b1CTRL[59] 1b0全局饱和模式浮点数转整数或整数转整数时的精度转换。不同类型转换支持的CastTrait类型取值表 6浮点转整数src dtypedst dtypelayoutModesatModemrgModeroundModehalfint4x2_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNChalfint8_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNChalfuint8_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNChalfint16_tRegLayout::UNKNOWNSatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNChalfint32_tRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNCbfloat16_tint32_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNCfloatint16_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNCfloatint32_tRegLayout::UNKNOWNSatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNCfloatint64_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNC表 7浮点转浮点src dtypedst dtypelayoutModesatModemrgModeroundModehifloat8_thalfRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNhifloat8_tfloatRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNfp8_e4m3fn_tfloatRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNfp8_e5m2_tfloatRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNfp8_e8m0_tbfloat16_tRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNfp4x2_e2m1_tbfloat16_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNfp4x2_e1m2_tbfloat16_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNhalfhifloat8_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_ROUND, RoundMode::HYBRIDhalfbfloat16_tRegLayout::UNKNOWNSatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNCbfloat16_thalfRegLayout::UNKNOWNSatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNCbfloat16_tfp4x2_e2m1_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNCbfloat16_tfp4x2_e1m2_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNCbfloat16_tfp8_e8m0_tRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNbfloat16_tfloatRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNfloathifloat8_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_ROUND, RoundMode::HYBRIDfloatfp8_e4m3fn_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_RINTfloatfp8_e5m2_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_RINTfloathalfRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_ODD, RoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNCfloatbfloat16_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNC表 8整数转浮点src dtypedst dtypelayoutModesatModemrgModeroundModeint4x2_thalfRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNint4x2_tbfloat16_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNint8_thalfRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNuint8_thalfRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNint16_thalfRegLayout::UNKNOWNSatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNCint16_tfloatRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNint32_tfloatRegLayout::UNKNOWNSatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNCint64_tfloatRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::CAST_RINT, RoundMode::CAST_ROUND, RoundMode::CAST_FLOOR, RoundMode::CAST_CEIL, RoundMode::CAST_TRUNC表 9整数转整数src dtypedst dtypelayoutModesatModemrgModeroundModeint4x2_tint16_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNint8_tint16_tRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNint8_tint32_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNuint8_tuint16_tRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNuint8_tuint32_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNint16_tint4x2_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::UNKNOWNint16_tuint8_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::UNKNOWNint16_tint32_tRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNint16_tuint32_tRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNuint16_tuint8_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::UNKNOWNuint16_tuint32_tRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNint32_tuint8_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::UNKNOWNint32_tint16_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::UNKNOWNint32_tuint16_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::UNKNOWNint32_tint64_tRegLayout::ZERO, RegLayout::ONESatMode::UNKNOWNMaskMergeMode::ZEROINGRoundMode::UNKNOWNuint32_tuint8_tRegLayout::ZERO, RegLayout::ONE, RegLayout::TWO, RegLayout::THREESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::UNKNOWNuint32_tint16_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::UNKNOWNuint32_tuint16_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::UNKNOWNint64_tint32_tRegLayout::ZERO, RegLayout::ONESatMode::NO_SAT, SatMode::SATMaskMergeMode::ZEROINGRoundMode::UNKNOWNfloat转hifloat8_t转换规则tmp2[31 : 0] f32_src_data[i][31 : 0]; Ev tmp2[30 : 23] - 8b01111111, thr tmp2[13 : 0]; if (Ev 128 tmp2[22 : 0] ! 23b0) then tmp3[7 : 0] HiF8NAN(8b10000000); else if ((Ev 128 tmp2[22 : 0] 23b0) || (Ev 15)) then tmp3[7 : 0] (tmp2[31] 1b0) ? HiF8inf(8b01101111) : HiF8-inf(8b11101111); else if (Ev -23) then tmp3[7 : 0] HiF8ZERO (8b00000000); else if (Ev -23) then if ((Half To Away Round) || (Hybrid Round {1’b1, tmp2[22 : 10]} thr)) then tmp3[7 : 0] (tmp2[31] 1b0) ? 8b00000001 : 8b10000001; // min subnormal else tmp3[7 : 0] HiF8ZERO(8b00000000); end if else if (Ev 0) then M tmp2[22 : 20], T A_bit tmp2[19], frac tmp2[19 : 6]; else if (Ev ±1) then M tmp2[22 : 20], T A_bit tmp2[19], frac tmp2[19 : 6]; else if (Ev ±[2, 3]) then M tmp2[22 : 20], T A_bit tmp2[19], frac tmp2[19:6]; else if (Ev ±[4, 7]) then M tmp2[22 : 21], T A_bit tmp2[20], frac tmp2[20 : 7]; else if (Ev ±[8, 15]) then M tmp2[22], T A_bit tmp2[21], frac tmp2[21 : 8]; else if (Ev [-16, -22]) then M Ev 23, T A_bit tmp2[22], frac tmp2[22 : 9]; // subnormal end if if (Ev ±[0, 3]) then if (T A_bit 1’b1) then M_tmp M 1, Ev Ev carry of M_tmp, M (carry of M_tmp) ? 0 : M_tmp; end if else if (Ev ±[4, 15]) then if (HALF To Away Round T A_bit 1’b1) || (Hybrid Round frac thr) then M_tmp M 1, Ev Ev carry of M_tmp, M (carry of M_tmp) ? 0 : M_tmp; end if else if (Ev [-16, -22]) then if ((Half To Away Round) T A_bit 1b1) || (Hybrid Round frac thr) then M_tmp Ev 23, Ev Ev 1, M (Ev -15) ? 0 : M_tmp; end if end if encode {tmp3[31], Ev, M} to tmp3[7 : 0] following HiF encoding rule; end if result[i][7 :0] saturation(tmp[7 : 0]) according to control bit;half转hifloat8_t转换规则tmp2[15 : 0] f16_src_data[i][15 : 0]; Ev tmp2[14 : 10] - 5b01111, thr {tmp2[0], 1’b1}; if (Ev 16 tmp2[9 : 0] ! 10b0) then tmp3[7 : 0] HiF8NAN(8b10000000); else if (Ev 16 tmp2[9:0] 10b0) (Ev 15) then tmp3[7 : 0] (tmp2[31] 1b0) ? HiF8inf(8b01101111) : HiF8-inf(8b11101111); else if (Ev -23) then tmp3[7 : 0] HiF8ZERO(8b00000000); else if (Ev -23) then if ((Half To Away Round) || (Hybrid Round {1’b1, tmp2[9]} thr)) then tmp3[7 : 0] (tmp2[31] 1b0) ? 8b00000001 : 8b10000001; // min subnormal else tmp3[7 : 0] HiF8ZERO(8b00000000); end if else if (Ev 0) then M tmp2[9 : 7], T A_bit tmp2[6], frac tmp2[6 : 5]; else if (Ev ±1) then M tmp2[9 : 7], T A_bit tmp2[6], frac tmp2[6 : 5]; else if (Ev ±[2, 3]) then M tmp2[9 : 7], T A_bit tmp2[6], frac tmp2[6 : 5]; else if (Ev ±[4, 7]) then M tmp2[9 : 8], T A_bit tmp2[7], frac tmp2[7 : 6]; else if (Ev ±[8, 15]) then M tmp2[9], T A_bit tmp2[8], frac tmp2[8 : 7]; else if (Ev [-16, -22]) then M Ev 23, T A_bit tmp2[9], frac tmp2[9 : 8]; // subnormal end if if (Ev ±[0, 3]) then if (T A_bit 1’b1) then M_tmp M 1, Ev Ev carry of M_tmp, M (carry of M_tmp) ? 0 : M_tmp; end if else if (Ev ±[4, 15]) then if (HALF To Away Round T A_bit 1’b1) || (Hybrid Round frac thr) then M_tmp M 1, Ev Ev carry of M_tmp, M (carry of M_tmp) ? 0 : M_tmp; end if else if (Ev [-16, -22]) then if ((Half To Away Round) T A_bit 1b1) || (Hybrid Round frac thr) then M_tmp Ev 23, Ev Ev 1, M (Ev -15) ? 0 : M_tmp; end if end if encode {tmp3[31], Ev, M} to tmp3[7 : 0] following HiF encoding rule; end if result[i][7 : 0] saturation(tmp3[7 : 0]) according to control bit;调用示例场景1位宽小转大以half→int32_t为例__simd_vf__ inline void CastVFF162S32(__ubuf__ half* xAddr, __ubuf__ int32_t* yAddr, uint32_t repeatTimes, uint16_t oneRepeatSize) { AscendC::Reg::MaskReg mask AscendC::Reg::CreateMaskint32_t, AscendC::Reg::MaskPattern::ALL(); AscendC::Reg::RegTensorhalf xReg; AscendC::Reg::RegTensorint32_t yReg; static constexpr AscendC::Reg::CastTrait castTrait { AscendC::Reg::RegLayout::ZERO, AscendC::Reg::SatMode::UNKNOWN, AscendC::Reg::MaskMergeMode::ZEROING, AscendC::RoundMode::CAST_FLOOR }; for (uint16_t i 0; i repeatTimes; i) { AscendC::Reg::LoadAlignhalf, AscendC::Reg::PostLiteral::POST_MODE_UPDATE, AscendC::Reg::LoadDist::DIST_UNPACK_B16(xReg, xAddr, oneRepeatSize); AscendC::Reg::Castint32_t, half, castTrait(yReg, xReg, mask); AscendC::Reg::StoreAlignint32_t, AscendC::Reg::PostLiteral::POST_MODE_UPDATE( yAddr, yReg, oneRepeatSize, mask); } }场景2位宽大转小以float→int16_t为例__simd_vf__ inline void CastVFF322S16(__ubuf__ float* xAddr, __ubuf__ int16_t* yAddr, uint32_t repeatTimes, uint16_t oneRepeatSize) { AscendC::Reg::MaskReg mask AscendC::Reg::CreateMaskfloat, AscendC::Reg::MaskPattern::ALL(); AscendC::Reg::RegTensorfloat xReg; AscendC::Reg::RegTensorint16_t yReg; static constexpr AscendC::Reg::CastTrait castTrait { AscendC::Reg::RegLayout::ZERO, AscendC::Reg::SatMode::SAT, AscendC::Reg::MaskMergeMode::ZEROING, AscendC::RoundMode::CAST_ROUND }; for (uint16_t i 0; i repeatTimes; i) { AscendC::Reg::LoadAlignfloat, AscendC::Reg::PostLiteral::POST_MODE_UPDATE(xReg, xAddr, oneRepeatSize); AscendC::Reg::Castint16_t, float, castTrait(yReg, xReg, mask); AscendC::Reg::StoreAlignint16_t, AscendC::Reg::PostLiteral::POST_MODE_UPDATE, AscendC::Reg::StoreDist::DIST_PACK_B32(yAddr, yReg, oneRepeatSize, mask); } }【免费下载链接】asc-devkit本项目是CANN 推出的昇腾AI处理器专用的算子程序开发语言原生支持C和C标准规范主要由类库和语言扩展层构成提供多层级API满足多维场景算子开发诉求。项目地址: https://gitcode.com/cann/asc-devkit创作声明：本文部分内容由AI辅助生成（AIGC），仅供参考
