verilog HDLBits刷题[Counters]“Countbcd ”---4-digit decimal counter

一、题目Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented.You may want to instantiate or modify some one-digit decade counters.Module Declarationmodule top_module ( input clk, input reset, // Synchronous active-high reset output [3:1] ena, output [15:0] q);二、分析输出16位每四位表示一个十进制数则低四位表示个位依次为十位百位千位每一位均满9进1.可先写一个四位的十位加法器带使能。再分别例化四次到顶层模块。三、代码实现module top_module ( input clk, input reset, // Synchronous active-high reset output [3:1] ena, output reg[15:0] q ); counter_4 inst1(clk,reset,1,q[3:0]); counter_4 inst2(clk,reset,ena[1],q[7:4]); counter_4 inst3(clk,reset,ena[2],q[11:8]); counter_4 inst4(clk,reset,ena[3],q[15:12]); assign ena[3](q[11:8]4d9)(q[7:4]4d9)(q[3:0]4d9); assign ena[2](q[7:4]4d9)(q[3:0]4d9); assign ena[1](q[3:0]4d9); endmodule module counter_4( input clk, input reset, // Synchronous active-high reset input ena, output reg[3:0] q ); always(posedge clk) if(reset)begin q4d0; end else if(ena)begin if(q4d9) q4d0; else qq4d1; end endmodule 或者 module top_module ( input clk, input reset, // Synchronous active-high reset output [3:1] ena, output [15:0] q); BCD_10 inst0(clk,reset,1,q[3:0]); BCD_10 inst1(clk,reset,ena[1],q[7:4]); BCD_10 inst2(clk,reset,ena[2],q[11:8]); BCD_10 inst3(clk,reset,ena[3],q[15:12]); assign ena[1](q[3:0]4d9); assign ena[2](q[7:4]4d9ena[1]); assign ena[3](q[11:8]4d9ena[2]); endmodule module BCD_10( input clk, input reset, input ena, output reg [3:0]q ); always (posedge clk)begin if (reset)begin q4d0; end else if(q4d9ena1b1)begin q4d0; end else if(ena1b1)begin qq4d1; end else qq; end endmodule四、时序