verilog HDLBits刷题[Finite State Machines]“Fsm1”---Simple FSM1(asynchronous reset)

1、题目This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.This exercise is the same as fsm1s, but using asynchronous reset.2、分析Moore 有限状态机输出只由当前状态决定3、代码module top_module( input clk, input areset, // Asynchronous reset to state B input in, output out);// parameter A1b0, B1b1; reg state, next_state; always (*) begin // This is a combinational always block case(state) A:next_statein?A:B; B:next_statein?B:A; endcase end always (posedge clk, posedge areset) begin // This is a sequential always block if(areset) stateB; else statenext_state; end assign out (state B); endmodule4、结果