verilog HDLBits刷题[Counters]“Count1to10”---Decade counter again

一、题目Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.Module Declarationmodule top_module ( input clk, input reset, output [3:0] q);二、分析同步高有效复位计数器变为1否则计数器从1加到10然后恢复为1再加到10三、代码实现module top_module ( input clk, input reset, output reg[3:0] q); always(posedge clk) if(reset) q4d1; else if(q4d10) q4d1; else qq4d1; endmodule 或者 module top_module ( input clk, input reset, output [3:0] q); reg [3:0]cnt; always (posedge clk)begin if(reset|cnt4d10) cnt4d1; else cntcnt4d1; end assign qcnt; endmodule四、时序