HDMI规范概述• TMDSTransition Minimized Different Signal3路数据通道、1路时钟通道• TMDS CharacterA 10bit TMDS-encode value1个TMDS Clock周期传输1个Character• TbitTime duration of a single bit carried across the TMDS data channels• TcharacterTime duration of a single TMDS character carriedacross the TMDS data channelsTcharacter 10 * Tbit• TMDS Clock Pixel Clock(at the default 24bit)24 bit mode: TMDS clock 1.0 x pixel clock30 bit mode: TMDS clock 1.25 x pixel clock36 bit mode: TMDS clock 1.5 x pixel clock48 bit mode: TMDS clock 2.0 x pixel clock25Mhz-340Mhz若视频格式需要的TMDS Clock小于25Mhz例如480i使用策略pixel-repetition scheme• DDC Display Data Channel用于Source和Sink交换配置/状态信息max rate 100Khz• HPD Hot Plug Detect用于热插拔检测/5V Power Signal检测at least 100ms• Pixel Size24 bit(default)、30bit、36bit、48bitEncoded in RGB、YCbCr 444 or YCbCr 422• Video8b -- 10bTransition Minimized Encoding• Audio and Auxiliary Data4b --10b类似Transition Minimized EncodingTMDS Error Reduction Encoding-4bit• Control Data2b -- 10bHsync/Vsync/CTL[0:3]Transition Maximized Encoding**HDMI电路设计需要参考的标准• Current Source电流源驱动常用接口芯片8mA~16mA• AVcc3.3V(±5%)DC耦合• Rt termination resistance50 ohms (±10%)与Z0匹配差分100ohms• VswingHigh level voltage AVccLow level voltage Avcc - Vswing**以TP1为例• DC CharacteristicSingle–ended standby output voltage AVcc±10mVSingle–ended output swing voltage 400mV ≤ Vswing ≤ 600mVSingle–ended high level output voltageif attached Sink supports only 165MHz :AVcc±10mVif attached Sink supports 165MHz :( AVcc – 200mV) ≤ VH ≤ (AVcc 10mV)Single-ended low level output voltageif attached Sink supports only 165MHz :(AVcc – 600mV) ≤ VL ≤ (AVcc – 400mV)if attached Sink supports 165MHz :( AVcc – 700mV) ≤ VL ≤ (AVcc – 400mV)• AC CharacteristicRise time / fall time (20%-80%) 75psec ≤ Rise time / fall timeIntra-Pair Skew at Source Connector Max 0.15*TbitInter-Pair Skew at Source Connector Max 0.20*TcharacterClock duty cycle Min40% / Average50% /Max 60%TMDS Differential Clock Jitter, max 0.25 Tbit• 5V Power SingalSource提供给Sink端TP1提供的5V范围Min 4.8V Max 5.3V要求Source最少的带载能力 55mA线缆最少的带载能力 50mA• An HDMI Source shall have 5V Power signal over-current protection of no more than 0.5A• SinkHigh voltage level Min 2.4V Max 5.3VLow voltage level Min 0V Max 0.4VOutput resistane 1K ohms±20%• SourceHigh voltage level Min 2.0V Max 5.3VLow voltage level Min 0V Max 0.8VHPD由Sink驱动为防止误判Source端必须要下拉,下拉电阻阻值要足够大。常用47K~100K重新配置需要拉低至少100ms• DDC/I2C使用I2C协议/ I2C Standard Mode/Max 100KhzSource端SCL/SDA上拉电阻 Min 1.5Kohms/Max 2KohmsSink端SCL上拉电阻 47Kohms电压 4.5V-5.5V• Maximum Capacitance of DDC lineHDMI Source 50pFCable Assembly 700pFHDMI Sink 50pF
